reZet80 PIONEER - 6-digit TIL311 display

Displaying RAM start address ("3800") and the amount of RAM in KiB ("02").

This is the 6-digit display card for the DISPLAY bus (see below).
It displays 6 hexadecimal numbers with TIL311 hexadecimal LED displays.
The decimal points (DP) are not used in the current version.
The card uses one I/O port in the 8-bit I/O space (see specs for I/O map and decoding).

Bill of materials:
- reZet80 PIONEER 6-digit TIL311 display card PCB
- 10-pin right-angled male connector
- 6x DIP-14 socket (optional)
- DIP-16 socket (optional)
- 6x TIL311 hexadecimal display
- 74LS138 demultiplexer
- 7x capacitor 100 nF

reZet80 DISPLAY bus specs:
This specification applies to both display cards, the one based on the TIL311 hexadecimal display and the alternative one built with 7-segment LED displays.
DISPB01: D7 (not used for TIL311 display)
DISPB02: D6 (not used for TIL311 display)
DISPB03: D5 (not used for TIL311 display)
DISPB04: D4 (not used for TIL311 display)
DISPB05: D3
DISPB06: D2
DISPB07: D1
DISPB08: D0
DISPB09: /IOSEL_7X
DISPB10: A8
DISPB11: A9
DISPB12: A10
DISPB13: GND
DISPB14: +5V

reZet80 PIONEER - 4 KiB ROM 2 KiB RAM card

Two 2 KiB ROM chips produce an amount of 4 KiB ROM, the maximum amount of ROM available on the card. The minimal ROM configuration is one chip of 2 KiB.
Populate U5 for ROM from 0000 to 07FF first. Populate U6 for ROM from 0800 to 0FFF.

Two 1024x4 SRAM chips produce an amount of 1 KiB RAM. This is the minimal RAM configuration.
Four SRAM chips can be installed in total providing a maximum of 2 KiB RAM.
Populate U1 and U3 for RAM from 3C00 to 3FFF first. Populate U2 and U4 for RAM from 3800 to 3BFF.

EEPROM chips can also be used although they were not available in the 70s (just in case an easier handling is more important than a 70s feeling).

Bill of materials:
- reZet80 PIONEER 4 KiB ROM 2 KiB RAM card PCB
- 40-pin right-angled male connector
- 2x (or 4x) DIP-18 socket
- 1x (or 2x) DIP-24 socket
- 2x (or 4x) 2114 SRAM (or compatible 1024x4 chips)
- 1x (or 2x) 2716 EPROM (or compatible 2 KiB chips)
- 3x (or 6x) capacitor 100 nF

reZet80 PIONEER - I/O map and decoding

The first 128 I/O ports (00-7F) are reserved for internal reZet80 use.
They are divided into 8 regions of 16 ports each:
00-0F, 10-1F, 20-2F, 30-3F, 40-4F, 50-5F, 60-6F and 70-7F.
These 8 regions will be further subdivided on demand.
The remaining 128 I/O ports are free to use: 80-FF.

The 74LS138 demultiplexer provides the following low-active signals:
- /IOSEL_0X (reserved for future use)
- /IOSEL_1X (reserved for future use)
- /IOSEL_2X (reserved for future use)
- /IOSEL_3X (reserved for future use)
- /IOSEL_4X (reserved for future use)
- /IOSEL_5X (alternative keypad)
- /IOSEL_6X (keypad or alternative keypad)
- /IOSEL_7X (6-digit display, TIL311 or 7-segment)

All I/O port addresses are given in hexadecimal notation.

Bill of materials:
- DIP-16 socket
- 74LS138 demultiplexer
- capacitor 100 nF

reZet80 PIONEER - memory timing

The Z80 uses 1.5 clock cycles for the opcode fetch during the M1 cycle and 2.5 clock cycles for all other read/write operations from/to ROM/RAM.
The maximum clock frequency for the NMOS Z80 is 2.5 MHz. At 2.5 MHz 1 clock cycle takes 400 ns, so 1.5 clock cycles mean 600 ns and 2.5 clock cycles last for 1000 ns.

The slowest 2716 memory chip has an access time of 450 ns. Adding 80 ns for 2 LSTTL demultiplexer stages needed to decode the ROM address results in a maximum total access time of 530 ns that is about 10% below the 600 ns needed for the M1 cycle.
Nevertheless, if possible use faster 2716 or compatible memory chips.

Decoding the RAM address takes 120 ns, 3 demultiplexer stages. The slowest 2114 memory chip has an access time of 450 ns. This sums up to 570 ns, far below 1000 ns.

The current reZet80 PIONEER specs:
- CPU: Z80 clocked at 2 MHz, 500 ns clock cycle
- RAM: 2114-1 (NEC 1024x4): 300 ns access time
- ROM: MB8516 (Fujitsu 2716 compatible): 450 ns access time
- ROM: K573PF2 (Russian 2716 clone): access time unknown

reZet80 PIONEER - memory map and address decoding

The 64 KiB address space of the Z80 is divided into 4 banks of 16 KiB each:
0000-3FFF, 4000-7FFF, 8000-BFFF, C000-FFFF.
Only the first 16 KiB bank is reserved for internal PIONEER use.
The remaining 48 KiB are free to use.

The first bank is divided into 8 regions of 2 KiB each:
0000-07FF, 0800-0FFF, 1000-17FF, 1800-1FFF, 2000-27FF, 2800-2FFF, 3000-37FF and 3800-3FFF.
The first 4 KiB are reserved for ROM.
The following 5 slots can host either ROM or RAM.
The last 2 KiB are provided for RAM and are further subdivided into 2 regions of 1 KiB each:
3800-3BFF and 3C00-3FFF.
Do not mix up slots with ROM and RAM and make sure that ROM is always located at the bottom and RAM at the top of the 16 KiB bank.

The 74LS138 and 74LS139 demultiplexers provide the following low-active signals:
- /MEMSEL_0000-3FFF (reserved for internal use)
- /MEMSEL_4000-7FFF
- /MEMSEL_8000-BFFF
- /MEMSEL_C000-FFFF
- /ROMCS_0000-07FF (reserved for 2 KiB ROM)
- /ROMCS_0800-0FFF (reserved for 2 KiB ROM)
- /RXMCS_1000-17FF (reserved for 2 KiB ROM or RAM)
- /RXMCS_1800-1FFF (reserved for 2 KiB ROM or RAM)
- /RXMCS_2000-27FF (reserved for 2 KiB ROM or RAM)
- /RXMCS_2800-2FFF (reserved for 2 KiB ROM or RAM)
- /RXMCS_3000-37FF (reserved for 2 KiB ROM or RAM)
- /MEMSEL_3800-3FFF (reserved for internal use
- /RAMCS_3800-3BFF (reserved for 1 KiB RAM)
- /RAMCS_3C00-3FFF (reserved for 1 KiB RAM)

All memory addresses are given in hexadecimal notation.

Bill of materials:
- 2x DIP-16 socket
- 74LS138 demultiplexer
- 74LS139 demultiplexer
- 2x capacitor 100 nF

reZet80 CPU bus specs R2

This is already the third version of the CPU bus specification (R2 for release 2 after R1 and R0).
It won't change again in the near future so I'll write down a few words about it covering also the Z80 and its data, address and control signals.
I think that retro enthusiasts and beginners who are new to the Z80 will be most interested in this post.

The Z80 CPU has 40 pins that make up the reZet80 CPU bus: 2 pins for the power supply (+5V and GND), 8 bidirectional data lines, 16 address lines and 14 control signals.
The Z80 is an 8-bit CPU because it can read or write 1 byte (8 bits) from/to memory or input/output port at once. Only as an aside, the Z80 can also handle 16 bits at once using its 16-bit registers but 1 word is transferred in two chunks.
There is also a mechanism of doing 16-bit I/O.
With 16 address lines the Z80 can address 64 kilobytes (KiB) of memory.
The 14 control signals are divided into 8 incoming and 6 outgoing signals.
All control signals except CLK (the clock signal) are active-low: a "/" in front of the signal name denotes an active-low signal. Active-low means that a logical zero on the line activates the signal.

The spec:
CPUB01: D7
CPUB02: D6
CPUB03: D5
CPUB04: D4
CPUB05: D3
CPUB06: D2
CPUB07: D1
CPUB08: D0
CPUB09: /IORQ
CPUB10: /MREQ
CPUB11: /HALT (or user-defined)
CPUB12: /NMI (or user-defined)
CPUB13: /INT (or user-defined)
CPUB14: /RD
CPUB15: /WR
CPUB16: /BUSACK (or user-defined)
CPUB17: /WAIT (or user-defined)
CPUB18: /BUSREQ (or user-defined)
CPUB19: /RESET
CPUB20: /M1
CPUB21: /RFSH (or user-defined)
CPUB22: CLK
CPUB23: GND
CPUB24: +5V
CPUB25: A0
CPUB26: A1
CPUB27: A2
CPUB28: A3
CPUB29: A4
CPUB30: A5
CPUB31: A6
CPUB32: A7
CPUB33: A8
CPUB34: A9
CPUB35: A10
CPUB36: A11
CPUB37: A12
CPUB38: A13
CPUB39: A14
CPUB40: A15

Some signals are optional and can be used for user-defined purposes.

For the reZet80 HWDK the data, address and control buses are also provided as separate buses:
CPUDATAB01: D7
CPUDATAB02: D6
CPUDATAB03: D5
CPUDATAB04: D4
CPUDATAB05: D3
CPUDATAB06: D2
CPUDATAB07: D1
CPUDATAB08: D0

CPUCTRLB01: /IORQ
CPUCTRLB02: /MREQ
CPUCTRLB03: /HALT
CPUCTRLB04: /NMI
CPUCTRLB05: /INT
CPUCTRLB06: /RD
CPUCTRLB07: /WR
CPUCTRLB08: /BUSACK
CPUCTRLB09: /WAIT
CPUCTRLB10: /BUSREQ
CPUCTRLB11: /RESET
CPUCTRLB12: /M1
CPUCTRLB13: /RFSH
CPUCTRLB14: CLK

CPUADDRB01: A0
CPUADDRB02: A1
CPUADDRB03: A2
CPUADDRB04: A3
CPUADDRB05: A4
CPUADDRB06: A5
CPUADDRB07: A6
CPUADDRB08: A7
CPUADDRB09: A8
CPUADDRB10: A9
CPUADDRB11: A10
CPUADDRB12: A11
CPUADDRB13: A12
CPUADDRB14: A13
CPUADDRB15: A14
CPUADDRB16: A15

reZet80 CPU card R2

This is the R2 update for the reZet80 CPU card.
Please check also the reZet80 CPU bus specs R2.

Bill of materials:
- reZet80 CPU R2 PCB
- 40-pin right-angled male connector
- DIP-40 socket (or ZIF-40 socket in order to easily exchange CPUs, optional)
- DIP-8 or DIP-14 socket (depending on oscillator size, optional)
- Z80 CPU (NMOS or CMOS, NMOS for the reZet80 PIONEER)
- oscillator (DIP-8 or DIP-14, 2 MHz for the reZet80 PIONEER)
- 6x resistor 4k7 (or 10k)
- 3x capacitor 100 nF
- 8x jumper wire (optional)

reZet80 to RC2014 bus adapter

The adapter provides a simple one-to-one mapping of the bus signals.

Well, with the exception of BUSACK, BUSREQ, HALT, NMI, RFSH and WAIT that are only available on the extended RC2014 bus. Together with INT these signals are available but optional (can be user-defined signals) on the reZet80 CPU bus.
The RC2014 signals RX and TX are not available on the reZet80 CPU bus.
The signals USER1, USER2, USER3 and USER4 correspond to the user-defined but optional reZet80 signals.

This adapter can accomodate one reZet80 card or one RC2014 card and can further be connected to a reZet80 or an RC2014 backplane.

The specs:
reZet80 CPU bus pin 01: D7 : RC2014 bus pin 34
reZet80 CPU bus pin 02: D6 : RC2014 bus pin 33
reZet80 CPU bus pin 03: D5 : RC2014 bus pin 32
reZet80 CPU bus pin 04: D4 : RC2014 bus pin 31
reZet80 CPU bus pin 05: D3 : RC2014 bus pin 30
reZet80 CPU bus pin 06: D2 : RC2014 bus pin 29
reZet80 CPU bus pin 07: D1 : RC2014 bus pin 28
reZet80 CPU bus pin 08: D0 : RC2014 bus pin 27
reZet80 CPU bus pin 09: /IORQ : RC2014 bus pin 26
reZet80 CPU bus pin 10: /MREQ : RC2014 bus pin 23
reZet80 CPU bus pin 11: /HALT : available only on extended RC2014 bus
reZet80 CPU bus pin 12: /NMI : available only on extended RC2014 bus
reZet80 CPU bus pin 13: /INT : RC2014 bus pin 22
reZet80 CPU bus pin 14: /RD : RC2014 bus pin 25
reZet80 CPU bus pin 15: /WR : RC2014 bus pin 24
reZet80 CPU bus pin 16: /BUSACK : available only on extended RC2014 bus
reZet80 CPU bus pin 17: /WAIT : available only on extended RC2014 bus
reZet80 CPU bus pin 18: /BUSREQ : available only on extended RC2014 bus
reZet80 CPU bus pin 19: /RESET : RC2014 bus pin 20
reZet80 CPU bus pin 20: /M1 : RC2014 bus pin 19
reZet80 CPU bus pin 21: /RFSH : available only on extended RC2014 bus
reZet80 CPU bus pin 22: CLK : RC2014 bus pin 21
reZet80 CPU bus pin 23: GND : RC2014 bus pin 17
reZet80 CPU bus pin 24: +5V : RC2014 bus pin 18
reZet80 CPU bus pin 25: A0 : RC2014 bus pin 16
reZet80 CPU bus pin 26: A1 : RC2014 bus pin 15
reZet80 CPU bus pin 27: A2 : RC2014 bus pin 14
reZet80 CPU bus pin 28: A3 : RC2014 bus pin 13
reZet80 CPU bus pin 29: A4 : RC2014 bus pin 12
reZet80 CPU bus pin 30: A5 : RC2014 bus pin 11
reZet80 CPU bus pin 31: A6 : RC2014 bus pin 10
reZet80 CPU bus pin 32: A7 : RC2014 bus pin 09
reZet80 CPU bus pin 33: A8 : RC2014 bus pin 08
reZet80 CPU bus pin 34: A9 : RC2014 bus pin 07
reZet80 CPU bus pin 35: A10 : RC2014 bus pin 06
reZet80 CPU bus pin 36: A11 : RC2014 bus pin 05
reZet80 CPU bus pin 37: A12 : RC2014 bus pin 04
reZet80 CPU bus pin 38: A13 : RC2014 bus pin 03
reZet80 CPU bus pin 39: A14 : RC2014 bus pin 02
reZet80 CPU bus pin 40: A15 : RC2014 bus pin 01

reZet80 PIONEER - 70s computing

This post describes the reZet80 PIONEER system.

The reZet80 PIONEER is an expandable modular stand-alone computer system that could have been built in the late 70s.
It is built from scratch and not a copy of any other Z80 system.
This project involves hardware and software development. I plan to develop and build every single pcb trace and every single bit of machine code by myself from scratch.
DIYIB: Doing it yourself is believing.
And WYDYIWYG: What you do yourself is what you get.

In its basic configuration the reZet80 PIONEER is equipped with 1 KiB of static RAM and 2 KiB of ROM containing a very simple debug monitor.
The maximum amount of onboard RAM and ROM are 2 KiB and 4 KiB, respectively.
The ROM can be upgraded to 14 KiB. RAM can be extended to 12 KiB and further increased by the addition of dynamic RAM.
Input and output are implemented by a 20-key keypad and a 6-digit display (either 7-segment LEDs or TIL311 LEDs that are more costly).
The mainboard also includes power supply sockets, on/off switch, reset switch and memory and I/O decoding circuitry (8 I/O ports).

An expansion bus, a video card, a memory cartridge, a sound card based on the AY-3-8910 chip and a joystick are planned to be added later.
Plans for the future also include to enhance the debug monitor and to provide a text adventure, at least one arcade clone, an assembler, a disassembler, a debugger and a C compiler.

The Zilog Z80 was introduced in 1976 in NMOS technology.
At the same time static memory chips like the 2125 (1K x 1 bit) and the 2114 (1K x 4 bit) were already available but were very expensive so memory was a scarce resource.
Dynamic RAM chips were more affordable back then. DRAM chips with a single +5V power supply like Intel's 2118 were available in 1979.
UV erasable 2 KiB PROMs with a single +5V power supply like Intel's 2716 were also available by 1977.
TI's TIL311 dates from 1972.
General Instrument's AY-3-8910 Programmable Sound Generator (PSG) was released in 1978.

reZet80 HWDK - hardware development kit

This post describes the reZet80 HWDK (hardware development kit).
This is a pure hardware project.

The reZet80 HWDK provides all the parts needed to build your Z80-based hardware projects: 3 different power sockets, on/off switch, a simple reset switch, 2 bus slots and 1 expansion slot to further extend the system and a large wire-wrap area that can be used for your custom-designed circuits.
Additionally, 38 data, address and control bus pins are located alongside the board to easily attach logic analyzer and oscilloscope probes.
One of the bus slots has to be populated with a reZet80 CPU board R2.
Only a 5 Volt power supply has to be connected to one of the 3 power sockets/connectors.

Bill of materials:
- 1x reZet80 HWDK R0 PCB
- 2x 40-pin female sockets (CPU bus slots)
- 1x 40-pin right-angled female socket (CPU bus expansion slot)
- 1x 2-pin male connector (power supply)
- 1x 8-pin male connector (CPU data bus)
- 1x 14-pin male connector (CPU control bus)
- 1x 16-pin male connector (CPU address bus)
- 1x tactile push button switch (reset)
- 1x on/off/on switch
- 1x female DC power supply socket
- 1x 2-pin screw connector (power supply)
- 1x red LED
- 1x resistor (choose according to LED specs)
- 3x capacitor 100 nF

RTC UPDATE

The RTC board now uses only one I/O port in the 8-bit I/O space, the 16 internal registers are addressed via 16-bit I/O.

8-digit 7-segment LED display

This is the 8-digit 7-segment display board for the I/O bus (see the specs for the reZet80 I/O bus).

The board displays 8 hexadecimal numbers and 3 additional characters (H, L and blank) plus 8 decimal points.

It uses only one I/O port in the 8-bit I/O space, the display digits are addressed via 16-bit I/O.

Bill of materials:
- PCB 12x8 cm (at least 40 rows)
- 40-pin right-angled male connector
- 4x 2-digit common cathode LED display (common anode also possible)
- DIP-16 socket
- 8x DIP-20 socket
- 74x138 demultiplexer
- 8x 74x374 8-bit flip-flop (or 74x574)
- 64x resistor (choose according to LED specs)
- capacitor 100 nF

20-key keypad

This is the 20-key keypad for the I/O bus (see the specs for the reZet80 I/O bus).

The keys '0' to 'F' are connected via a 4-bit matrix.
Additionally 4 special keys (ENTER, BACK, ESC and SHIFT) are available.

Bill of materials:
- 20-key keypad
- PCB 5x7 cm (at least 22 rows)
- 22-pin right-angled male connector
- 4-pin male connector
- 8-pin male connector
- 4-wire cable female/female
- 8-wire cable female/female
- DIP-14 socket
- 2x DIP-20 socket
- 74x04 hex inverter
- 2x 74x373 octal latch
- 8x resistor 4k7
- capacitor 100 nF

I/O board UPDATE

For I/O-demanding systems preparations have been made to optionally divide the regions 10h-1fh and 20h-2fh into 16 single I/O ports each.
The I/O bus now adds a row of 40 separate I/O or user-defined pins to the CPU bus.

reZet80 I/O bus:
IOB01: D7
IOB02: D6
IOB03: D5
IOB04: D4
IOB05: D3
IOB06: D2
IOB07: D1
IOB08: D0
IOB09: IOREQ
IOB10: MREQ
IOB11: NMI or user-defined
IOB12: INT or user-defined
IOB13: RD
IOB14: WR
IOB15: BUSACK or user-defined
IOB16: WAIT or user-defined
IOB17: BUSREQ or user-defined
IOB18: RESET
IOB19: M1
IOB20: RFSH or user-defined
IOB21: GND
IOB22: +5V
IOB23: A0
IOB24: A1
IOB25: A2
IOB26: A3
IOB27: A4
IOB28: A5
IOB29: A6
IOB30: A7
IOB31: A8
IOB32: A9
IOB33: A10
IOB34: A11
IOB35: A12
IOB36: A13
IOB37: A14
IOB38: A15
IOB39: CLK
IOB40: HALT or user-defined

IOB41: IOSEL_00_0F or user-defined
IOB42: IOSEL_10_1F or user-defined
IOB43: IOSEL_20_2F or user-defined
IOB44: IOSEL_30_3F or user-defined
IOB45: IOSEL_40_4F or user-defined
IOB46: IOSEL_50_5F or user-defined
IOB47: IOSEL_60_6F or user-defined
IOB48: IOSEL_70_7F or user-defined
IOB49: IOSEL_10 or user-defined
IOB50: IOSEL_11 or user-defined
IOB51: IOSEL_12 or user-defined
IOB52: IOSEL_13 or user-defined
IOB53: IOSEL_14 or user-defined
IOB54: IOSEL_15 or user-defined
IOB55: IOSEL_16 or user-defined
IOB56: IOSEL_17 or user-defined
IOB57: IOSEL_18 or user-defined
IOB58: IOSEL_19 or user-defined
IOB59: IOSEL_1A or user-defined
IOB60: IOSEL_1B or user-defined
IOB61: IOSEL_1C or user-defined
IOB62: IOSEL_1D or user-defined
IOB63: IOSEL_1E or user-defined
IOB64: IOSEL_1F or user-defined
IOB65: IOSEL_20 or user-defined
IOB66: IOSEL_21 or user-defined
IOB67: IOSEL_22 or user-defined
IOB68: IOSEL_23 or user-defined
IOB69: IOSEL_24 or user-defined
IOB70: IOSEL_25 or user-defined
IOB71: IOSEL_26 or user-defined
IOB72: IOSEL_27 or user-defined
IOB73: IOSEL_28 or user-defined
IOB74: IOSEL_29 or user-defined
IOB75: IOSEL_2A or user-defined
IOB76: IOSEL_2B or user-defined
IOB77: IOSEL_2C or user-defined
IOB78: IOSEL_2D or user-defined
IOB79: IOSEL_2E or user-defined
IOB80: IOSEL_2F or user-defined

In total 47 bus pins can be utilized for I/O or user-defined purposes.

64 KiB ROM / RAM board UPDATE

I did some modifications to the board that restrict the activity of the memory chips, yet the functionality remains unchanged.

The /CE pin of the ROM and the /CE1 pin of the RAM were active even on I/O instructions although no harm was caused to the overall functionality of the system as the /MEMRD and /MEMWR signals were only active on memory accesses.

Now all three pins /CE, /CE1 and /CE2 become active only on memory accesses and I got rid of the 74x04 inverter.

Another small modification: I connected both A15 and A16 of the SRAM chip to GND, so now the lower 32 KiB get accessed.