reZet80 CPU bus specs R2

This is already the third version of the CPU bus specification (R2 for release 2 after R1 and R0).
It won't change again in the near future so I'll write down a few words about it covering also the Z80 and its data, address and control signals.
I think that retro enthusiasts and beginners who are new to the Z80 will be most interested in this post.

The Z80 CPU has 40 pins that make up the reZet80 CPU bus: 2 pins for the power supply (+5V and GND), 8 bidirectional data lines, 16 address lines and 14 control signals.
The Z80 is an 8-bit CPU because it can read or write 1 byte (8 bits) from/to memory or input/output port at once. Only as an aside, the Z80 can also handle 16 bits at once using its 16-bit registers but 1 word is transferred in two chunks.
There is also a mechanism of doing 16-bit I/O.
With 16 address lines the Z80 can address 64 kilobytes (KiB) of memory.
The 14 control signals are divided into 8 incoming and 6 outgoing signals.
All control signals except CLK (the clock signal) are active-low: a "/" in front of the signal name denotes an active-low signal. Active-low means that a logical zero on the line activates the signal.

The spec:
CPUB01: D7
CPUB02: D6
CPUB03: D5
CPUB04: D4
CPUB05: D3
CPUB06: D2
CPUB07: D1
CPUB08: D0
CPUB09: /IORQ
CPUB10: /MREQ
CPUB11: /HALT (or user-defined)
CPUB12: /NMI (or user-defined)
CPUB13: /INT (or user-defined)
CPUB14: /RD
CPUB15: /WR
CPUB16: /BUSACK (or user-defined)
CPUB17: /WAIT (or user-defined)
CPUB18: /BUSREQ (or user-defined)
CPUB19: /RESET
CPUB20: /M1
CPUB21: /RFSH (or user-defined)
CPUB22: CLK
CPUB23: GND
CPUB24: +5V
CPUB25: A0
CPUB26: A1
CPUB27: A2
CPUB28: A3
CPUB29: A4
CPUB30: A5
CPUB31: A6
CPUB32: A7
CPUB33: A8
CPUB34: A9
CPUB35: A10
CPUB36: A11
CPUB37: A12
CPUB38: A13
CPUB39: A14
CPUB40: A15

Some signals are optional and can be used for user-defined purposes.

For the reZet80 HWDK the data, address and control buses are also provided as separate buses:
CPUDATAB01: D7
CPUDATAB02: D6
CPUDATAB03: D5
CPUDATAB04: D4
CPUDATAB05: D3
CPUDATAB06: D2
CPUDATAB07: D1
CPUDATAB08: D0

CPUCTRLB01: /IORQ
CPUCTRLB02: /MREQ
CPUCTRLB03: /HALT
CPUCTRLB04: /NMI
CPUCTRLB05: /INT
CPUCTRLB06: /RD
CPUCTRLB07: /WR
CPUCTRLB08: /BUSACK
CPUCTRLB09: /WAIT
CPUCTRLB10: /BUSREQ
CPUCTRLB11: /RESET
CPUCTRLB12: /M1
CPUCTRLB13: /RFSH
CPUCTRLB14: CLK

CPUADDRB01: A0
CPUADDRB02: A1
CPUADDRB03: A2
CPUADDRB04: A3
CPUADDRB05: A4
CPUADDRB06: A5
CPUADDRB07: A6
CPUADDRB08: A7
CPUADDRB09: A8
CPUADDRB10: A9
CPUADDRB11: A10
CPUADDRB12: A11
CPUADDRB13: A12
CPUADDRB14: A13
CPUADDRB15: A14
CPUADDRB16: A15