I/O board UPDATE

For I/O-demanding systems preparations have been made to optionally divide the regions 10h-1fh and 20h-2fh into 16 single I/O ports each.
The I/O bus now adds a row of 40 separate I/O or user-defined pins to the CPU bus.

reZet80 I/O bus:
IOB01: D7
IOB02: D6
IOB03: D5
IOB04: D4
IOB05: D3
IOB06: D2
IOB07: D1
IOB08: D0
IOB09: IOREQ
IOB10: MREQ
IOB11: NMI or user-defined
IOB12: INT or user-defined
IOB13: RD
IOB14: WR
IOB15: BUSACK or user-defined
IOB16: WAIT or user-defined
IOB17: BUSREQ or user-defined
IOB18: RESET
IOB19: M1
IOB20: RFSH or user-defined
IOB21: GND
IOB22: +5V
IOB23: A0
IOB24: A1
IOB25: A2
IOB26: A3
IOB27: A4
IOB28: A5
IOB29: A6
IOB30: A7
IOB31: A8
IOB32: A9
IOB33: A10
IOB34: A11
IOB35: A12
IOB36: A13
IOB37: A14
IOB38: A15
IOB39: CLK
IOB40: HALT or user-defined

IOB41: IOSEL_00_0F or user-defined
IOB42: IOSEL_10_1F or user-defined
IOB43: IOSEL_20_2F or user-defined
IOB44: IOSEL_30_3F or user-defined
IOB45: IOSEL_40_4F or user-defined
IOB46: IOSEL_50_5F or user-defined
IOB47: IOSEL_60_6F or user-defined
IOB48: IOSEL_70_7F or user-defined
IOB49: IOSEL_10 or user-defined
IOB50: IOSEL_11 or user-defined
IOB51: IOSEL_12 or user-defined
IOB52: IOSEL_13 or user-defined
IOB53: IOSEL_14 or user-defined
IOB54: IOSEL_15 or user-defined
IOB55: IOSEL_16 or user-defined
IOB56: IOSEL_17 or user-defined
IOB57: IOSEL_18 or user-defined
IOB58: IOSEL_19 or user-defined
IOB59: IOSEL_1A or user-defined
IOB60: IOSEL_1B or user-defined
IOB61: IOSEL_1C or user-defined
IOB62: IOSEL_1D or user-defined
IOB63: IOSEL_1E or user-defined
IOB64: IOSEL_1F or user-defined
IOB65: IOSEL_20 or user-defined
IOB66: IOSEL_21 or user-defined
IOB67: IOSEL_22 or user-defined
IOB68: IOSEL_23 or user-defined
IOB69: IOSEL_24 or user-defined
IOB70: IOSEL_25 or user-defined
IOB71: IOSEL_26 or user-defined
IOB72: IOSEL_27 or user-defined
IOB73: IOSEL_28 or user-defined
IOB74: IOSEL_29 or user-defined
IOB75: IOSEL_2A or user-defined
IOB76: IOSEL_2B or user-defined
IOB77: IOSEL_2C or user-defined
IOB78: IOSEL_2D or user-defined
IOB79: IOSEL_2E or user-defined
IOB80: IOSEL_2F or user-defined

In total 47 bus pins can be utilized for I/O or user-defined purposes.

64 KiB ROM / RAM board UPDATE

I did some modifications to the board that restrict the activity of the memory chips, yet the functionality remains unchanged.

The /CE pin of the ROM and the /CE1 pin of the RAM were active even on I/O instructions although no harm was caused to the overall functionality of the system as the /MEMRD and /MEMWR signals were only active on memory accesses.

Now all three pins /CE, /CE1 and /CE2 become active only on memory accesses and I got rid of the 74x04 inverter.

Another small modification: I connected both A15 and A16 of the SRAM chip to GND, so now the lower 32 KiB get accessed.