It connects all 40 CPU pins to the bus.
The objective of the CPU bus design is to do without intersections except for the data pins (they are out of order anyway) and the halt pin that is of no interest in the current design stage (see specs for CPU bus below).
5 resistors 4k7 are used to pull the signals BUSREQ, INT, NMI, RESET and WAIT high.
Additionally an oscillator is available on the board.
With the help of 2 jumpers 2 different clock speeds and 3 configurations
are possible:
- CPU board oscillator for the entire system
- An external oscillator for the entire system
- CPU board oscillator only for the CPU and an external oscillator for the rest of the system
Currently a 1 MHz oscillator is used.
reZet80 CPU bus:
CPUB01: D7
CPUB02: D6
CPUB03: D5
CPUB04: D4
CPUB05: D3
CPUB06: D2
CPUB07: D1
CPUB08: D0
CPUB09: IOREQ
CPUB10: MREQ
CPUB11: NMI
CPUB12: INT
CPUB13: RD
CPUB14: WR
CPUB15: BUSACK
CPUB16: WAIT
CPUB17: BUSREQ
CPUB18: RESET
CPUB19: M1
CPUB20: RFSH
CPUB21: GND
CPUB22: +5V
CPUB23: A0
CPUB24: A1
CPUB25: A2
CPUB26: A3
CPUB27: A4
CPUB28: A5
CPUB29: A6
CPUB30: A7
CPUB31: A8
CPUB32: A9
CPUB33: A10
CPUB34: A11
CPUB35: A12
CPUB36: A13
CPUB37: A14
CPUB38: A15
CPUB39: CLK
CPUB40: HALT
Bill of materials:
- PCB 12x8 cm (at least 40 rows)
- 40-pin right-angled male connector
- DIP-40 socket (or ZIF-40 socket in order to easily exchange CPUs)
- DIP-8 or DIP-14 socket (depending on oscillator size)
- 20 MHz Z80 CPU DIP-40
- 20 MHz oscillator (DIP-8 or DIP-14)
- 5x resistor 4k7
- capacitor 100 nF
- 2x jumper
