reZet80 deMon (debug Monitor)

This is the reZet80 deMon (debug Monitor) R0 (release zero).
It's the software that runs on the reZet80 DEV.

The amount of ROM and RAM are checked and displayed first (shall be 20H and 20H for the 64 KiB board, "H" for hexadecimal).

Then the date and time are displayed (will be 2000-00-00 and 00:00:00 on first startup).

After pressing any key (the right arrow tells you to do so) you are provided with a prompt.

The only available command is "DWYYMMDDHHMMSS" to set the date and time.
  D:  set "D"ate / time command
  W:  day of the week (0 = Sunday, 6 = Saturday)
  YY: year (20YY, 00 - 99)
  MM: month (01 - 12)
  DD: day (01 - 31)
  HH: hour (00 - 24, only 24-hour format is supported for now)
  MM: minute (00 - 59)
  SS: second (00 - 59)

No plausibility checks are done.

12-hour format and a few other functions are not implemented yet.

Due to the battery backup the system clock continues to work after system shutdown.

And that's it for R0.

Documentation including schematics, images and source code: GitHub

Reset board UPDATE

The TL7705 supervisor and 2 accompanying capacitors are now optional.

If you omit the TL7705 you have to manually press the reset button every time you power up the system (more work, less hardware).

CPU board and CPUBUS specs UPDATE

The signals BUSACK, BUSREQ, HALT, NMI, RFSH and WAIT are optional on the CPUBUS, so these pins can be used as user-defined.

The CLK signal is pulled high to ensure the right voltage for the CPU in NMOS/TTL and mixed systems (CMOS CPU and NMOS CRTC for example).

reZet80 CPU bus:
CPUB01: D7
CPUB02: D6
CPUB03: D5
CPUB04: D4
CPUB05: D3
CPUB06: D2
CPUB07: D1
CPUB08: D0
CPUB09: IOREQ
CPUB10: MREQ
CPUB11: NMI | user-defined
CPUB12: INT
CPUB13: RD
CPUB14: WR
CPUB15: BUSACK | user-defined
CPUB16: WAIT | user-defined
CPUB17: BUSREQ | user-defined
CPUB18: RESET
CPUB19: M1
CPUB20: RFSH | user-defined
CPUB21: GND
CPUB22: +5V
CPUB23: A0
CPUB24: A1
CPUB25: A2
CPUB26: A3
CPUB27: A4
CPUB28: A5
CPUB29: A6
CPUB30: A7
CPUB31: A8
CPUB32: A9
CPUB33: A10
CPUB34: A11
CPUB35: A12
CPUB36: A13
CPUB37: A14
CPUB38: A15
CPUB39: CLK
CPUB40: HALT | user-defined

The simplest variant of a backplane

Just a Veroboard in Eurocard format (but any format would do) with 40-pin female sockets soldered to it.

A 100 mm Eurocard accomodates 39 strips (rows).
That's OK for now as the HALT signal is of no interest in the current design stage.

The second stripboard you see is the I/O bus I'm experimenting with, so just forget about it.

16x1 LCD display

This is the LCD 16x1 board for the I/O bus (see the specs for the reZet80 I/O bus).

It is similar to the 20x4 LCD board because all LCD displays provide the same parallel interface:

 1: GND
 2: +5V
 3: V0
 4: RS   [A0]
 5: R/W  [/WR]
 6: E    [IOSEL inverted]
 7: DB0  [D0]
 8: DB1  [D1]
 9: DB2  [D2]
10: DB3  [D3]
11: DB4  [D4]
12: DB5  [D5]
13: DB6  [D6]
14: DB7  [D7]
15: VDD backlight
16: GND backlight

A variable 4k7 resistor connected to V0 is used to set the display contrast. Another resistor is connected between LCD pin 16 and GND if VDD backlight is less than 5V, otherwise connect pin 16 directly to GND.
Please always check your LCD display specs!

Bill of materials:
- PCB 5x7 cm (at least 23 rows)
- 23-pin right-angled male connector
- DIP-14 socket
- DIP-20 socket
- 74x04 hex inverter
- 74x245 octal bidirectional transceiver
- resistor 6.8R (choose according to the LCD specs)
- variable resistor 4k7
- capacitor 100 nF

amber display from my Yamaha FB-01

4-bit real-time clock (RTC)

This is the RTC 72421 board for the I/O bus (see the specs for the reZet80 I/O bus).

The RTC-72421 is a 4-bit real-time clock with a parallel interface.
It provides 16 registers that store time (hour, minute, second) and calendar (year, month, day, day of the week).
Battery backup, automatic leap year correction and a fixed-period interrupt are also included.

Bill of materials:
- PCB 5x7 cm (at least 22 rows)
- 22-pin right-angled male connector
- DIP-18 narrow socket
- RTC-72421
- CR2032 3V battery
- battery holder
- 2x schotthy diode IN5817
- capacitor 100 nF
- capacitor 47 uF

16-key keypad

This is the hexadecimal keypad for the I/O bus (see the specs for the reZet80 I/O bus).

The keys '0' to 'F' are connected via a 4-bit matrix.

Bill of materials:
- 16-key (hexadecimal) keypad
- PCB 5x7 cm (at least 22 rows)
- 22-pin right-angled male connector
- 2x 4-pin male connector
- 2x 4-wire cable female/female
- DIP-14 socket
- 2x DIP-20 socket
- 74x04 hex inverter
- 2x 74x373 octal latch
- 4x resistor 4k7
- capacitor 100 nF

Connecting to a 20x4 LCD display

This is the LCD 20x4 board for the I/O bus (see the specs for the reZet80 I/O bus).

20x4 (20 characters, 4 lines) LCD modules provide a parallel interface and are wired as follows:

 1: GND
 2: +5V
 3: V0
 4: RS  [A0]
 5: R/W  [/WR]
 6: E  [IOSEL inverted]
 7: DB0  [D0]
 8: DB1  [D1]
 9: DB2  [D2]
10: DB3  [D3]
11: DB4  [D4]
12: DB5  [D5]
13: DB6  [D6]
14: DB7  [D7]
15: VDD backlight
16: GND backlight

A variable 4.7k resistor connected to V0 is used to set the display contrast.
A 3.3R resistor is connected between LCD pin 16 and GND if VDD backlight is less than 5V (please check your specs!), otherwise connect pin 16 directly to GND.

Bill of materials:
- PCB 5x7 cm (at least 23 rows)
- 23-pin right-angled male connector
- DIP-14 socket
- DIP-20 socket
- 74x04 hex inverter
- 74x245 octal bidirectional transceiver
- resistor 3.3R (choose according to the LCD specs)
- variable resistor 4k7
- capacitor 100 nF

playing around with the RTC

The I/O board

This is the I/O board for the I/O bus (see specs for I/O bus below).
 
The first 128 I/O ports (00h-7fh) are reserved for internal reZet80 use.
They are divided into 8 regions of 16 ports each by a demultiplexer:

00h-0fh, 10h-1fh, 20h-2fh, 30h-3fh, 40h-4fh, 50h-5fh, 60h-6fh and 70h-7fh.

The 8 regions will be further subdivided on demand.

8 LEDs flash while the corresponding I/O region is selected.

The remaining 128 I/O ports are free to use: 80h-ffh.

reZet80 I/O bus:
IOB01: D7
IOB02: D6
IOB03: D5
IOB04: D4
IOB05: D3
IOB06: D2
IOB07: D1
IOB08: D0
IOB09: IOREQ
IOB10: MREQ
IOB11: NMI
IOB12: INT
IOB13: RD
IOB14: WR
IOB15: BUSACK
IOB16: WAIT
IOB17: BUSREQ
IOB18: RESET
IOB19: M1
IOB20: RFSH
IOB21: GND
IOB22: +5V
IOB23: A0
IOB24: A1
IOB25: A2
IOB26: A3
IOB27: A4
IOB28: A5
IOB29: A6
IOB30: A7
IOB31: IOSEL_00_0F
IOB32: IOSEL_10_1F
IOB33: IOSEL_20_2F
IOB34: IOSEL_30_3F
IOB35: IOSEL_40_4F
IOB36: IOSEL_50_5F
IOB37: IOSEL_60_6F
IOB38: IOSEL_70_7F
IOB39: CLK
IOB40: HALT

Bill of materials:
- PCB 5x7 cm (at least 22 rows)
- 22-pin right-angled male connector
- 8-pin male connector
- DIP-16 socket
- DIP-20 socket
- 74x138 demultiplexer
- 74x240 octal buffer
- 8x LED red
- 8x resistor 220R (choose according to the LED specs)
- capacitor 100 nF

Reset the reZet80 system

This is the reset board for the CPU bus (see the specs for the reZet80 CPU bus).

The sole purpose of the reset board is to generate the RESET signal that initializes the Z80 CPU.

Additionally a power-on reset of about 3 ms is triggered when power is applied to the system. This frees us from manually pressing the reset button on start up.

Bill of materials:
- PCB 4x6 cm (at least 5 rows)
- 5-pin right-angled male connector
- DIP-8 socket
- TL7705 supervisor
- tactile push button switch
- resistor 4k7
- capacitor 100 nF
- capacitor 220 nF

 
The single step circuit on the left side of the board is not part of the reset circuitry. The same applies to the power switch and the red power LED.

A simple 64 KiB ROM / RAM board

This is the 64 KiB ROM / RAM board for the CPU bus (see the specs for the reZet80 CPU bus).

For simplicity the address space is divided into 2 parts having 32 KiB ROM in the lower half (0000h-7fffh) and 32 KiB RAM in the upper half (8000h-ffffh).

The address line A15 serves as ROM selector (/ROMSEL) and the inverted signal as RAM selector (/RAMSEL).
The memory read (/MEMRD) and memory write (/MEMWR) signals are also generated on the board.

A 128 KiB SRAM chip is used instead of a 32 KiB chip.

Bill of materials:
- PCB 12x8 cm (at least 40 rows)
- 40-pin right-angled male connector
- wide DIP-32 socket
- wide DIP-28 socket (or ZIF-40 socket in order to easily exchange ROM chips)
- 2x DIP-14 socket
- 128 KiB SRAM (LP621024D, KM681000B, DS1245Y, ...)
- 32 KiB ROM (AT28C256, ..., can be PROM, EPROM, EEPROM or FLASH)
- 74x04 hex inverter
- 74x32 quad 2-input OR gate
- capacitor 100 nF

A minimalistic Z80 CPU board

The Z80 is the heart of the system and the CPU board is quite simple.
It connects all 40 CPU pins to the bus.

The objective of the CPU bus design is to do without intersections except for the data pins (they are out of order anyway) and the halt pin that is of no interest in the current design stage (see specs for CPU bus below).

5 resistors 4k7 are used to pull the signals BUSREQ, INT, NMI, RESET and WAIT high.

Additionally an oscillator is available on the board.
With the help of 2 jumpers 2 different clock speeds and 3 configurations
are possible:
- CPU board oscillator for the entire system
- An external oscillator for the entire system
- CPU board oscillator only for the CPU and an external oscillator for the rest of the system
Currently a 1 MHz oscillator is used.



reZet80 CPU bus:
CPUB01: D7
CPUB02: D6
CPUB03: D5
CPUB04: D4
CPUB05: D3
CPUB06: D2
CPUB07: D1
CPUB08: D0
CPUB09: IOREQ
CPUB10: MREQ
CPUB11: NMI
CPUB12: INT
CPUB13: RD
CPUB14: WR
CPUB15: BUSACK
CPUB16: WAIT
CPUB17: BUSREQ
CPUB18: RESET
CPUB19: M1
CPUB20: RFSH
CPUB21: GND
CPUB22: +5V
CPUB23: A0
CPUB24: A1
CPUB25: A2
CPUB26: A3
CPUB27: A4
CPUB28: A5
CPUB29: A6
CPUB30: A7
CPUB31: A8
CPUB32: A9
CPUB33: A10
CPUB34: A11
CPUB35: A12
CPUB36: A13
CPUB37: A14
CPUB38: A15
CPUB39: CLK
CPUB40: HALT

Bill of materials:
- PCB 12x8 cm (at least 40 rows)
- 40-pin right-angled male connector
- DIP-40 socket (or ZIF-40 socket in order to easily exchange CPUs)
- DIP-8 or DIP-14 socket (depending on oscillator size)
- 20 MHz Z80 CPU DIP-40
- 20 MHz oscillator (DIP-8 or DIP-14)
- 5x resistor 4k7
- capacitor 100 nF
- 2x jumper

reZet80 DEV - a barebone Z80 development system

This blog post describes the reZet80 DEV system.

First of all, reZet80 stands for "Reset me back to the 80s with the Z80".

The reZet80 DEV is a barebone (minimalistic) development system for the low-level Z80 retro enthusiast.
Its main use is programming in Assembler using the Z80 processor.
The system resembles the Z80 machines of the late 70s and early 80s.
But it is built from scratch and not a copy of any other Z80 system.

The reZet80 DEV builds the foundation for all my coming reZet80 projects.
It involves hardware and software development.
I plan to develop and build every single pcb trace and every single bit of machine code by myself from scratch.
Doing it yourself is believing (DIYIB)!
And: What you do yourself is what you get (WYDYIWYG)!

The reZet80 DEV includes a Z80 CPU, a motherboard, a power supply with on/off and reset switches, memory, I/O circuitry, a display, a keypad and of course the monitor software.
Pieces of hardware like LCD that were not available back then are also part of the system.
All peripherals will be connected directly to the Z80 and no other processor like for example AVR, PIC or ARM will be used, neither as a bootloader nor to attach peripherals to.

Two LCD displays are available: 16x1 and 20x4 characters.
To double the fun factor a real-time clock is included.

All we can do in the beginning is enter and display hexadecimal numbers but the full Z80 instruction set is ready to use.
The DEV will run my own monitor software.

This system will be enhanced on demand for convenience.

List of modules:
- Backplane
- Reset switch & power-on reset board
- Z80 CPU board
- 64 KiB ROM/RAM board
- I/O board
- LCD 16x1
- LCD 20x4
- Hexadecimal keypad (16 keys)
- RTC 72421